Interrupt and Exception Handling Mechanisms in Operating Systems

Interrupt and Exception Handling Mechanisms in Operating Systems

Interrupts and exceptions are core mechanisms in operating systems that enable the CPU to work in coordination with external devices and handle urgent events. They allow the CPU to pause the current task, switch to handling higher-priority events, and resume the original task after processing is complete.

1. Basic Concepts and Classification

  • Interrupt: A signal from an external hardware device to the CPU, occurring asynchronously (unrelated to the execution of the current instruction)

    • Hardware interrupts: Keyboard input, timer expiration, disk I/O completion
    • Maskable interrupts: Can be ignored via interrupt mask bits (e.g., network packet arrival)
    • Non-maskable interrupts: Emergency events (e.g., memory errors, power failures)

  • Exception: Special conditions detected synchronously by the CPU during instruction execution

    • Fault: Repairable errors (e.g., page fault, division by zero error)
    • Trap: Actively triggered exceptions (e.g., system calls, breakpoint debugging)
    • Abort: Irrecoverable errors (e.g., hardware failure)

2. Hardware Support for Interrupt Handling

  • Interrupt Controller: Receives signals from multiple interrupt sources, performs priority arbitration, and sends an interrupt request to the CPU
  • Interrupt Vector Table: An array storing entry addresses of interrupt handler routines, with a unique number for each interrupt type
  • Program Status Word: A special register containing control flags such as interrupt mask bits and privilege levels

3. Complete Interrupt Handling Process
(1) Interrupt Trigger Phase

  • The device sends a signal to the interrupt controller via an interrupt request line
  • The interrupt controller masks lower-priority interrupts and sends an INTR signal to the CPU

(2) Context Saving Phase

  • After completing the current instruction execution, the CPU detects the interrupt signal
  • Pushes key registers such as the current program counter and program status word onto the kernel stack
  • Disables interrupt response (sets interrupt mask bits to prevent nested interrupts)

(3) Interrupt Identification Phase

  • The CPU reads the interrupt vector number from the interrupt controller (e.g., 0x21 for keyboard interrupt)
  • Queries the corresponding interrupt service routine address via the Interrupt Descriptor Table

(4) Context Switching Phase

  • Saves the state of all general-purpose registers to the Process Control Block
  • Switches to kernel mode, using kernel stack space
  • Updates the page table base register to point to the kernel address space

(5) Interrupt Handling Phase

  • Executes the Interrupt Service Routine (ISR)
  • For device interrupts: Reads device status registers and performs data transfer
  • For page faults: Allocates physical page frames and updates page table entries

(6) Context Restoration Phase

  • Restores all register values from the kernel stack
  • Restores the program status word and program counter
  • Switches back to user mode (if the original program was running in user mode)

4. Special Exception Handling Processes

  • Page Fault Exception:

    1. Checks the legality of the access address
    2. Allocates a physical page frame and establishes a mapping
    3. Re-executes the instruction that triggered the exception

  • System Call Trap:

    1. Actively triggered via a specific instruction (e.g., int 0x80 on x86)
    2. Looks up the service routine based on the system call number
    3. Performs parameter validation and permission checks

5. Key Design Points

  • Interrupt Nesting: High-priority interrupts can interrupt the handling of lower-priority interrupts
  • Interrupt Sharing: Requires polling to check interrupt sources when multiple devices share an interrupt line
  • Bottom-Half Mechanisms: Divides interrupt handling into urgent top-half and deferrable bottom-half (e.g., soft interrupts, task queues)
  • Timer Interrupt: Periodic interrupts implement time-slice round-robin scheduling and system timing

6. Case Study (Keyboard Input Interrupt)

  1. A key press triggers the keyboard controller interrupt
  2. The CPU saves the execution context of the current text editor
  3. Reads the keyboard scan code and converts it to ASCII code
  4. Stores the character in the input buffer
  5. Wakes up the process waiting for input
  6. Resumes the text editor execution, displaying the character on the screen

This mechanism ensures that the operating system can promptly respond to external events while maintaining the isolation and stability of the multitasking environment.