Interrupt Handling Mechanism in Operating Systems

Description: Interrupts are a core mechanism for operating systems to achieve concurrent execution and respond to external events. When a hardware device requires CPU processing, it sends an interrupt signal. The CPU then suspends the currently executing program, switches to a specific interrupt handler, and resumes the original program after handling the interrupt. Understanding the entire process of interrupt handling is fundamental to comprehending how operating systems manage hardware and implement multitasking.

Detailed Explanation:

1. Basic Concept and Types of Interrupts

   • Why are interrupts needed? Without interrupts, the CPU would need to continuously poll various hardware devices to check if they require service. This method is highly inefficient and wastes significant CPU time. The interrupt mechanism allows hardware devices to actively "notify" the CPU when needed, enabling the CPU to focus on executing other tasks until interrupted.
   • Types of Interrupts:
     • Hardware Interrupts: Generated by external hardware devices, such as keyboard presses, mouse movements, disk I/O completion, or network packet arrival. This is the most typical type of interrupt.
     • Exceptions (a type of software interrupt): Triggered by abnormal events detected by the CPU during instruction execution, such as division by zero errors, page faults, or illegal memory access. Exceptions are usually synchronous and related to specific instructions.
     • Traps (a type of software interrupt): Actively requested by programs, with the most typical example being system calls. Programs use a special instruction (e.g., int 0x80 or syscall) to trap into the kernel and request services from the operating system.

2. Core Data Structure for Interrupt Handling: Interrupt Vector Table

   • What is it? The interrupt vector table is a specific area in memory, which can be thought of as a "jump table" or "function pointer array."
   • Function: Each entry in the table corresponds to an interrupt number. The entry for each interrupt number stores the entry address of the corresponding interrupt handler.
   • How it works: When the CPU receives an interrupt signal and obtains its interrupt number, it immediately consults the interrupt vector table, finds the corresponding entry, and jumps to the address specified in that entry to begin execution. This is similar to a company's switchboard receiving calls for different extensions (interrupt numbers) and directly transferring them to the corresponding department (interrupt handler).

3. Detailed Steps of Interrupt Handling
   Interrupt handling is a precise process accomplished through hardware and software collaboration. The diagram below clearly illustrates the entire process from interrupt occurrence to completion:

flowchart TD
    A[CPU Executes Current Program] --> B{Interrupt Occurs?}
    B -- Yes --> C[Finish Current Instruction Execution]
    B -- No --> A

    C --> D[Disable Interrupts<br>Save Critical Context<br>(PSW, PC, etc.)]
    D --> E[Identify Interrupt Source<br>Obtain Interrupt Number]
    E --> F[Consult Interrupt Vector Table<br>Load ISR Address]
    F --> G[Jump to ISR]

    subgraph ISR [Interrupt Service Routine]
        G --> H[Protect Remaining Context<br>(General-Purpose Registers, etc.)]
        H --> I[Enable Interrupts<br>(Allow Nesting)]
        I --> J[Execute Core Processing Logic]
        J --> K[Disable Interrupts<br>(Prepare for Return)]
        K --> L[Restore Context]
    end

    L --> M[Execute Interrupt Return Instruction]
    M --> N[Restore Original Program PSW and PC]
    N --> A

Below, we explain each key step in the process in detail:

*   **Step 1: Interrupt Occurrence and Request**
    A hardware device (e.g., a disk) completes a data read and sends an interrupt request signal to the CPU via the interrupt controller.

*   **Step 2: CPU Responds to Interrupt**
    The CPU does not respond to interrupts at any arbitrary point during instruction execution. It always checks for pending interrupt requests **after the current instruction finishes** and before fetching the next instruction. If an interrupt request is present, it begins responding.

*   **Step 3: Save Context**
    This is the most critical step, ensuring the accurate restoration of the interrupted program after interrupt handling. Context saving is done in two stages:
    *   **Automatic saving by hardware**: The CPU hardware automatically pushes the current **Program Status Word (PSW)** and **address of the next instruction** onto the kernel stack. The PSW contains crucial information such as condition codes and interrupt enable/disable flags, while the PC (Program Counter) points to the address of the instruction that should have been executed next. This step guarantees correct eventual return.
    *   **Saving other registers by software**: At the beginning of the interrupt service routine, assembly instructions are used to push the values of **general-purpose registers** and any other context that might be altered onto the stack.

*   **Step 4: Identify Interrupt Source and Jump**
    The CPU obtains the **interrupt number** from the interrupt controller, queries the **interrupt vector table** to find the entry address of the corresponding **interrupt service routine**, and jumps to that address to execute.

*   **Step 5: Execute Interrupt Service Routine**
    This is where the core task of handling the interrupt occurs, typically written by the operating system kernel. For example, for a keyboard interrupt, the ISR reads the key scan code from the keyboard controller, converts it to a character code, and places it in an area called the "input buffer." During execution, the ISR may **re-enable interrupts** to allow interrupt nesting for handling more urgent interrupts.

*   **Step 6: Restore Context and Return**
    After the ISR finishes execution:
    *   First, **disable interrupts** to prevent interference during context restoration.
    *   Then, pop the previously saved general-purpose register values from the stack to restore the context.
    *   Finally, execute a special **interrupt return instruction**. This instruction **pops the PC and PSW previously saved automatically by the hardware from the stack**, causing the CPU to jump back to the interrupted program and continue execution with its original state.

Summary: The interrupt mechanism is the cornerstone for operating systems to respond to external events and achieve multitasking concurrency. It routes interrupts via the "interrupt vector table" and achieves seamless switching through "context saving/restoration," allowing the CPU to efficiently manage all hardware devices without polling and handle various internal exceptions. The entire process demonstrates the exquisitely precise collaboration between hardware and operating system software.